Project Summary: Widefield imaging and spatial multiplexing are crucial to advancing the field of neuroscience. Current imagers do not offer the speed and versatility needed for calcium or voltage imaging experiments. In the case of lifetime imaging the functionality is completely lacking in CMOS imagers. The problem is more subtle than it seems because it is not just a matter of brute force speed-up through technology. Speed increases come with large amounts of power dissipation and the need for faster data interfaces. One imaging technique with the potential to solve this issue is the single photon avalanche detector (SPAD). SPADs by virtue of operation result in digital pulse practically eliminating read noise that commonly plagues regular imagers. However, SPAD imagers till date have not seen widespread use due to low pixel density. One of the greatest advantages of the SPAD imager is its ability to perform time correlated measurements, enabling lifetime imaging. Lifetime imagers can yield absolute quantitative measurements not possible with regular imaging modalities. However, the current SPAD imagers take seconds to minutes to compute a lifetime image, much too slow for neural imaging. We propose to overcome these fundamental barriers by innovating at the device, architecture and packaging levels. Our proposed approach utilizes a transistor amplified SPAD design coupled with in pixel analog counting and lifetime estimation. These two innovations make it possible to read the pixel level data at a slower rate, while maintaining a fast frame rate. We additionally propose a new chip level integration approach which packages the imager die and processing die in a silicon package enabling reading from subarrays. This approach enables the imager to maintain the frame rate of the pixel subarray as the pixel density scales. Finally, we demonstrate the advantages of our imager by imaging dendritic activity, both in intensity and lifetime imaging modes, in neural cultures at unprecedented spatiotemporal scales.