Emerging memory technologies, which facilitate both analog and digital in-memory computations, have captured the attention of commercial and defense sectors as promising replacements for traditional von Neumann computing architectures commonly used in edge sensors. Over the past five years, numerous publications have illustrated the pivotal role of these advanced memory arrays in supporting intelligent systems capable of real-time learning and swift adaptation to changing conditions. Nonetheless, the adoption of these technologies is hampered by the limited availability of mainstream fabrication processes. Currently, TSMC is the predominant provider, which imposes significant cost barriers for research groups eager to develop and test new circuit designs. This innovative digital twin (DT) is designed to validate new designs and propel research and development in this emerging field. It promises to revolutionize design processes across various technical specifications, including frequency bands, signal-to-noise ratios, and spectrum classifiers. The DT has a scalable architecture that facilitates the integration of extensive library models for memory devices and supports these devices across a broad spectrum of material systems and operational scenarios. The potential benefits of this DT, with sensor technology and computational model for advanced receivers, extends to enhancing national security by providing significant advancements in secure communications and threat detectio