Combinatorial optimization (CO) problems are pervasive under the hood of modern life. CO problems underlie artificial intelligence, autonomous driving, logistics in healthcare/power grids/transportation, robotic maneuvering, wireless communications, error tolerant data storage, and many other societally important technologies. In recent years, new ways to solve these problems (using "analog oscillator" mechanisms) have emerged that promise far greater solution effectiveness than current techniques can achieve---if appropriate semiconductor "chip" implementations can be devised. The main goal of this project is to design, fabricate and demonstrate such chip implementations, along with systems that utilize them. Achieving this goal will lead to improved efficiencies solving a variety of societally important combinatorial optimization problems. Dissemination and training are also important components of this project. The specific scheme being investigated is called oscillator Ising machines (OIMs). OIM simulations have predicted high success rates solving various combinatorial optimization problems. However, integrated circuit (IC) implementations have had difficulty delivering such predicted levels of performance. In this project, the investigators will identify technological reasons for this discrepancy, and devise measures to address them. A key feature is an IC fabric that supports programmable interconnectivity between analog units. The impact of noise and device variab