This award supports research on three-dimensional (3D) chip design methods that advance national prosperity by enabling more capable and energy-efficient computing systems. Modern software applications, such as Artificial Intelligence (AI) large-language models, require orders-of-magnitude improvements in performance and energy efficiency beyond what traditional transistor scaling can deliver, and a growing share of energy is wasted shuttling data between processors and memory rather than performing useful computation. 3D chip integration can overcome this challenge by co-locating computation and memory within a single chip footprint. However, it introduces a combinatorial design landscape with tightly coupled tradeoffs across devices, interconnects, packaging, thermal management, and overall hardware architecture. This project will develop a hierarchical System-Technology Co-Optimization (STCO) framework powered by fast and accurate virtual models of devices, circuits, packaging, and applications. These models will enable rapid exploration of 3D chip design alternatives and, uniquely, will derive required 3D chip technology targets directly from application-level performance needs. The outcome will be new design methods, open-source design tools, and hardware prototypes that enable more energy-efficient 3D chip computing systems, strengthening U.S. leadership in advanced semiconductor technologies and workforce development. Education activities will integrate 3D chip design modules into hands-on fabrication and advanced chip-design courses, establish technician training in semiconductor manufacturing, and engage local K-12 students through interactive outreach programs. The technical goal is a hierarchical system-technology co-optimization (STCO) toolchain that jointly explores device choices, packaging, and chip architecture for 3D integrated circuits. The project will (1) build calibrated models for logic and memory device technologies used in 3D stacks by com